←Leaderboard/Software Engineering/verilog-generator
Last commit on August 25, 2026·Created on May 8, 2026

Eriemon/verilog-generator

“Automates the generation and validation of synthesizable Verilog-2001 RTL files.”
Combined rank
#632
across all skills
In Software Engineering
#54
category rank
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TL;DR

This skill assists FPGA and ASIC engineers in creating, refactoring, and reviewing readable hardware descriptions. It structures the transition from design contracts to RTL through a rigorous pipeline of requirement planning and specification documentation.

Hardware verification engineers can use the tool to plan testbench scaffolds and perform ASIC-quality reviews, utilizing Vivado or xsim for validation to ensure design integrity.

WHO IT'S FOR
FPGA / ASIC engineers
generate synthesizable Verilog-2001 RTL files
Hardware verification engineers
plan testbench scaffolds and validate RTL
Digital design architects
perform ASIC-quality reviews of RTL designs
RTL maintenance engineers
repair and refactor existing Verilog code
Repository contents

1 skill file

Categories
Software EngineeringPrimary
AutomationDeveloper Tooling
Compatible AgentsThe repository documents support for these agents. The skills may also work with other agents that can load SKILL.md files, but they may need some setup or small changes.
ClaudeCodexGemini CLIDeepSeek

Use this skill

Follow the documented setup, then try a first task.

Codex via PowerShell

Installs: Installs the readable-verilog-generator skill from the complete versioned v2.0.0 release payload. · Codex

Before you start
  • A versioned v2.0.0 release payload containing SKILL.md, install.ps1, and the configured RELEASE_RECEIPT.json
  • PowerShell
  • An available configured Python candidate: python3 or python

Platform: A platform capable of running PowerShell; the target Harness is Codex.

Run from: The v2.0.0 release directory containing SKILL.md and install.ps1

  1. From the release directory, preview the Codex installation. This dry run does not write files.

    .\install.ps1 -Platform codex -DryRun -Json

  2. After reviewing the preview, run the actual Codex installation from the same release directory. An existing target is automatically backed up before replacement.

    .\install.ps1 -Platform codex -Json
installer.manifest.env ↗ · Checked Sep 18, 2026SKILL.md ↗ · Checked Sep 18, 2026README.md ↗ · Checked Sep 18, 2026

Give it something to do.

Author’s example

Review an existing RTL design without modifying it

Uses readable-verilog-generator

  • The Verilog .v file or files to review
  • Any relevant testbench or integration context
  • The questions or risks you want emphasized
使用 $readable-verilog-generator 审查这份 RTL 的复位行为、握手错误、位宽问题、
命名、注释和综合风险。只输出审查结果，不修改文件。
README-CN.md ↗ · Checked Sep 18, 2026SKILL.md ↗ · Checked Sep 18, 2026
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