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Last commit on July 5, 2026·Created on May 8, 2026
Eriemon/verilog-generator
“Generates Verilog-2001 RTL that must pass a strict deliverable gate before delivery.”
Combined rank
#405
across all skills
In Software Engineering
#40
category rank
Stars
212
+2.4% in last 7d
Forks
12
+9.1% in last 7d
Watchers
3
0.0% in last 7d
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Description
This skill produces synthesizable Verilog-2001 RTL with ASIC-quality review, static lint, and a mandatory formatter-backed deliverable gate. It helps FPGA design engineers, RTL verification engineers, and hardware design teams generate new RTL, analyze existing designs, run verify-repair loops, and enforce the erie_strict style profile. The skill also provides self-checking testbench scaffolds, semantic comparison, and controlled improvement flows for existing RTL assets.
WHO IT'S FOR
FPGA Design Engineers
generate synthesizable Verilog RTL and validate
RTL Verification Engineers
create testbench scaffolds and verify-repair loops
Hardware Design Teams
enforce strict RTL style and conventions
AI Hardware Automation Engineers
integrate Verilog generation API into pipelines
30 Days of GitHub Stars
+22 stars↑ 12.8% monthly change
Jul 7Jul 14Jul 21Jul 28Aug 5
Compatibility & Install1 Skill · 1 Compatible agent · 3 categories · 1 install path
Compatible agents
❯Codex
Categories
Software EngineeringAutomationDeveloper Tooling
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